A computer system typically employs a system bus to exchange information between devices of the system, including a central processing unit (CPU), a host memory and an input/output (I/O) adapter. The exchange of information is typically accomplished via a bus transaction, which consists of an address transfer over the bus followed by a data transfer. A bus transaction may be a "write" transaction or a "read" transaction, depending upon the direction of the data flow with respect to a receiver, e.g., the host memory. For example, a read transaction transfers data from memory to the CPU or I/O adapter, and a write transaction transfers data to the memory. Typically, a bus transaction involves more than one data transfer over the bus.
During a bus transaction, information may be exchanged among the devices of the system according to a "master-slave" arrangement. A bus master is a device that initiates the bus transaction, while a bus slave, i.e., the device addressed by the master, responds to the transaction request. Examples of a bus master may be a CPU or an I/O adapter, whereas a bus slave may be a memory unit or an I/O unit, e.g., a disk drive.
Computer systems having multiple bus masters, each of which may request use of the bus, typically employ a central arbitration system to decide which bus master is granted access to the bus. For example, a bus master is granted access to and control of the system bus in accordance with an ordering procedure defined by the arbitration access policy. Typically, the access policy provides for only one bus master at a time. Consequently, a bus master requesting control of the bus at a time when another device has access must wait until the current bus master relinquishes control before transferring information. This latent period may adversely affect bus utilization and reduce system performance, particularly if the current bus slave requires a significant amount of time to process a request.
One approach to increasing bus utilization is to restructure use of the bus such that a bus master issues a request to a bus slave and then relinquishes total control of the bus. The slave responds to the master at a later time after it has completed the request. Although this approach, called a pended bus arrangement, significantly increases the utilization of the bus, the circuitry needed to implement the pended bus protocols Within the bus devices are costly and complex.
Accordingly, it is among the objects of this invention to provide a simple, low-cost I/O adapter capable of operating on a pended system bus.
Another object of the invention is to provide a simple, low-cost I/O adapter having multiple microprocessor-based devices for controlling multiple I/O units, wherein each device is capable of operating on a pended system bus.
Yet another object of the invention is to provide a multiplexed address/data signal bus for interconnecting multiple microprocessor-based devices, each of which may concurrently function as a bus master on the signal bus.